| 1. | If there is no instruction cache , this subroutine may be a no - op
如果在你的目标机上，没有指令缓存，则可能不做任何操作。 |
| 2. | Instruction to invalidate the instruction cache line that will contain the modified instruction
指令，使将要存放修改后指令的指令高速缓存行无效。 |
| 3. | On sparc and sparclite only , write this subroutine to flush the instruction cache , if any , on your target machine
只在sparc和sparclite平台上，这一功能调用用来刷新指令缓存。 |
| 4. | It is a risc microprocessor , has a six - stage pipeline , with separated data cache and instruction cache
银河ts - 1采用典型的risc结构，六级流水线，具有独立的指令cache和数据cache 。 |
| 5. | In order to gain more performance improvement 8k data cache and 8k instruction cache are used in ck510
这些改进使c - core性能大大超过m - core 。整数运算能力是嵌入式cpu中重要的性能指标。 |
| 6. | The fetcher generates a fetch address for fetching a cache block from the instruction cache containing instructions to be executed
指令读取器产生读取位址以供快取记忆体读取快取区块内的指令。 |
| 7. | On target machines that have instruction caches , gdb requires this function to make certain that the state of your program is stable
在有指令缓存的目标机上， gdb需要这一函数，以确定你的程序的状态是稳定的。 |
| 8. | An instruction cache miss will occur when fetching this instruction , resulting in the fetching of the modified instruction from storage
当取这个指令时会发生指令高速缓存失败，结果就会从存储器中取得修改后的指令。 |
| 9. | And in fact , the problem is exacerbated by the fact that a media app pushes data through the data cache much faster than a static app pushes code through the instruction cache
事实上，这是由于动态媒体程序需要以远远高于静态程序填充指令的速度来填充数据。 |
| 10. | This paper presents the logic circuit design of ccu for lx - 1164 cpu chip , for ccu , data and instructions are stored in separate data and instruction caches
本人有幸在夏宏博士的指导下参加这一工程，承担lx ? 1164cpu的高速缓存控制器( ccu )的逻辑设计和功能仿真。 |
